A load detection circuit is a circuit that generates an indicator signal to determine whether the load capacitor is higher or lower than a pre-specified value. This has to be done in the presence of an unknown resistive load. The load can be an external load or an internal load to the chip. The indicator signal can then be used in applications for various purposes, such as, but not limited to, stabilizing a power management unit.
FIG. 1(A) shows a prior art load detection circuit. The supply is defined as VDD (101), the ground is defined as GND (102), the output indicator signal is defined as HC (103), the clock signal is defined as CLK (104), and the reference voltage signals are defined as REF1 (105) and REF2 (106). The implementation shown in FIG. 1(A) represents a load detection circuit with a variable current source (107), a variable gain amplifier (VGA, 108), two comparators (109 and 110), and two counters (111 and 112).
In each clock cycle, the counters increment their counts by one. The current source (107) initially starts to charge the load capacitor CL (113) in the presence of the load resistor RL (114). As a result, the output voltage Vout starts to increase with time. After a fixed time period, the gain of the variable gain amplifier (108) is increased. At the same time, counter (111) is incrementing with time based on the clock. This continues until the variable gain amplifier (VGA, 108) output reaches REF1 (105). This is detected by a comparator (109). The counter final count is proportional to the load resistor RL (114). After that, the current source (107) is incremented and CL (113) is recharged. At the same time, the counter (112) is incrementing with time based on the clock. Once the output voltage Vout reaches a pre-specified value, the counter stops counting at a final count. The pre-specified value is determined by REF2 (106) and detected by a comparator (110). The final count is proportional to the load capacitor CL (113). In other words, a higher final count corresponds to a larger load capacitance value, and vice versa. Accordingly, the final count represents an estimate of the load capacitance of CL (113).
As depicted in FIG. 1(B), the timing diagram of the prior art load detection circuits shows a variable time load detection methodology. The discharge phase (115) is fixed in time, while the resistor detection phase (116) is variable in time, and the capacitor detection phase time duration (117) depends on the value of the load capacitor.
The prior art analog circuit (100) depicted in FIG. 1(A) uses a load detection circuit to detect whether an output capacitance is higher than a pre-specified value, but the overall time that it takes to perform the load detection operation (e.g. tdis+tch+trch) is variable. Therefore, this approach does not support a fixed-time load detection mechanism. Therefore, there is a need for better implementation for load detection with a pre-determined and predictable duration time.